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41.
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Design Verification and Test of Digital VLSI Circuits: High Level Design Representation / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering High Level Design Representation
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Publication details: Guwahati Indian Insitiute of Technology
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42.
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Design Verification and Test of Digital VLSI Circuits: Transformations for High Level Synthesis / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Transformations for High Level Synthesis
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Publication details: Guwahati Indian Insitiute of Technology
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43.
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Design Verification and Test of Digital VLSI Circuits: "Introduction to HLS: Scheduling, Allocation and Binding Problem" / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering "Introduction to HLS: Scheduling, Allocation and Binding Problem"
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Publication details: Guwahati Indian Insitiute of Technology
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44.
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Design Verification and Test of Digital VLSI Circuits: Scheduling Algorithms-1 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Scheduling Algorithms-1
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Publication details: Guwahati Indian Insitiute of Technology
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45.
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Design Verification and Test of Digital VLSI Circuits: Scheduling Algorithms-2 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Scheduling Algorithms-2
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Publication details: Guwahati Indian Insitiute of Technology
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46.
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Design Verification and Test of Digital VLSI Circuits: Binding and Allocation Algorithms / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Binding and Allocation Algorithms
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Publication details: Guwahati Indian Insitiute of Technology
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47.
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Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-1 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Two level Boolean Logic Synthesis-1
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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48.
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Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-2 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Two level Boolean Logic Synthesis-2
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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49.
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Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-3 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Two level Boolean Logic Synthesis-3
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50.
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Design Verification and Test of Digital VLSI Circuits: Heuristic Minimization of Two-Level Circuits / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Heuristic Minimization of Two-Level Circuits
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51.
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Design Verification and Test of Digital VLSI Circuits: Finite State Machine Synthesis / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Finite State Machine Synthesis
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52.
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Design Verification and Test of Digital VLSI Circuits: Multilevel Implementation / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Multilevel Implementation
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53.
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Design Verification and Test of Digital VLSI Circuits: Introduction to formal methods for design verification / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to formal methods for design verification
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54.
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Design Verification and Test of Digital VLSI Circuits: Temporal Logic: Introduction and Basic Operators / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Temporal Logic: Introduction and Basic Operators
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55.
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Design Verification and Test of Digital VLSI Circuits: Syntax and Semantics of CTL / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Syntax and Semantics of CTL
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56.
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Design Verification and Test of Digital VLSI Circuits: Syntax and Semantics of CTL � Continued / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Syntax and Semantics of CTL � Continued
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57.
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Design Verification and Test of Digital VLSI Circuits: Equivalence between CTL Formulas / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Equivalence between CTL Formulas
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58.
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Design Verification and Test of Digital VLSI Circuits: Introduction to Model Checking / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to Model Checking
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59.
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Design Verification and Test of Digital VLSI Circuits: Model Checking Algorithms I / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Model Checking Algorithms I
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60.
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Design Verification and Test of Digital VLSI Circuits: Model Checking Algorithms II / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Model Checking Algorithms II
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Publication details: Guwahati Indian Insitiute of Technology
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