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5461.
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Computational Geometry: Geometric Set Cover / Sandeep Sen by Series: NPTEL Lecture Series. Computer Science and Engineering Geometric Set Cover
Material type: Computer file Computer file; Format: electronic
Publication details: Delhi Indian Insitiute of Technology
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5462.
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Computational Geometry: Geometric Set Cover / Sandeep Sen by Series: NPTEL Lecture Series. Computer Science and Engineering Geometric Set Cover
Material type: Computer file Computer file; Format: electronic
Publication details: Delhi Indian Insitiute of Technology
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5463.
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Computational Geometry: Shape Represenatation / Sandeep Sen by Series: NPTEL Lecture Series. Computer Science and Engineering Shape Represenatation
Material type: Computer file Computer file; Format: electronic
Publication details: Delhi Indian Insitiute of Technology
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5464.
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Computational Geometry: Shape Comparision / Sandeep Sen by Series: NPTEL Lecture Series. Computer Science and Engineering Shape Comparision
Material type: Computer file Computer file; Format: electronic
Publication details: Delhi Indian Insitiute of Technology
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5465.
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Design Verification and Test of Digital VLSI Circuits: Introduction to Digital VLSI Design Flow / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to Digital VLSI Design Flow
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5466.
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Design Verification and Test of Digital VLSI Circuits: High Level Design Representation / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering High Level Design Representation
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5467.
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Design Verification and Test of Digital VLSI Circuits: Transformations for High Level Synthesis / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Transformations for High Level Synthesis
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5468.
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Design Verification and Test of Digital VLSI Circuits: "Introduction to HLS: Scheduling, Allocation and Binding Problem" / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering "Introduction to HLS: Scheduling, Allocation and Binding Problem"
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5469.
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Design Verification and Test of Digital VLSI Circuits: Scheduling Algorithms-1 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Scheduling Algorithms-1
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5470.
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Design Verification and Test of Digital VLSI Circuits: Scheduling Algorithms-2 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Scheduling Algorithms-2
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5471.
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Design Verification and Test of Digital VLSI Circuits: Binding and Allocation Algorithms / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Binding and Allocation Algorithms
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5472.
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Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-1 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Two level Boolean Logic Synthesis-1
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5473.
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Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-2 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Two level Boolean Logic Synthesis-2
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5474.
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Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-3 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Two level Boolean Logic Synthesis-3
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5475.
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Design Verification and Test of Digital VLSI Circuits: Heuristic Minimization of Two-Level Circuits / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Heuristic Minimization of Two-Level Circuits
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5476.
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Design Verification and Test of Digital VLSI Circuits: Finite State Machine Synthesis / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Finite State Machine Synthesis
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5477.
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Design Verification and Test of Digital VLSI Circuits: Multilevel Implementation / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Multilevel Implementation
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5478.
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Design Verification and Test of Digital VLSI Circuits: Introduction to formal methods for design verification / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to formal methods for design verification
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5479.
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Design Verification and Test of Digital VLSI Circuits: Temporal Logic: Introduction and Basic Operators / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Temporal Logic: Introduction and Basic Operators
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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5480.
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Design Verification and Test of Digital VLSI Circuits: Syntax and Semantics of CTL / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Syntax and Semantics of CTL
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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