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641.
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Advanced Hydraulics: Channel Transitions-part 3 / Suresh A Kartha by Series: NPTEL Lecture Series. Civil Engineering Channel Transitions-part 3
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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642.
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Advanced Hydraulics: Application of Momentum Principles / Suresh A Kartha by Series: NPTEL Lecture Series. Civil Engineering Application of Momentum Principles
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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643.
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Advanced Hydraulics: Pumps-1 / Suresh A Kartha by Series: NPTEL Lecture Series. Civil Engineering Pumps-1
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Publication details: Guwahati Indian Insitiute of Technology
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644.
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Advanced Hydraulics: Turbines-part 3(pumps,turbines) / Suresh A Kartha by Series: NPTEL Lecture Series. Civil Engineering Turbines-part 3(pumps,turbines)
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Publication details: Guwahati Indian Insitiute of Technology
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645.
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Advanced Hydraulics: Turbines,Cavitation / Suresh A Kartha by Series: NPTEL Lecture Series. Civil Engineering Turbines,Cavitation
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Publication details: Guwahati Indian Insitiute of Technology
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646.
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Design Verification and Test of Digital VLSI Circuits: Introduction to Digital VLSI Design Flow / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to Digital VLSI Design Flow
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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647.
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Design Verification and Test of Digital VLSI Circuits: High Level Design Representation / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering High Level Design Representation
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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648.
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Design Verification and Test of Digital VLSI Circuits: Transformations for High Level Synthesis / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Transformations for High Level Synthesis
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Publication details: Guwahati Indian Insitiute of Technology
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649.
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Design Verification and Test of Digital VLSI Circuits: "Introduction to HLS: Scheduling, Allocation and Binding Problem" / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering "Introduction to HLS: Scheduling, Allocation and Binding Problem"
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Publication details: Guwahati Indian Insitiute of Technology
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650.
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Design Verification and Test of Digital VLSI Circuits: Scheduling Algorithms-1 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Scheduling Algorithms-1
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651.
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Design Verification and Test of Digital VLSI Circuits: Scheduling Algorithms-2 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Scheduling Algorithms-2
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Publication details: Guwahati Indian Insitiute of Technology
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652.
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Design Verification and Test of Digital VLSI Circuits: Binding and Allocation Algorithms / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Binding and Allocation Algorithms
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Publication details: Guwahati Indian Insitiute of Technology
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653.
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Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-1 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Two level Boolean Logic Synthesis-1
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Publication details: Guwahati Indian Insitiute of Technology
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654.
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Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-2 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Two level Boolean Logic Synthesis-2
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Publication details: Guwahati Indian Insitiute of Technology
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655.
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Design Verification and Test of Digital VLSI Circuits: Two level Boolean Logic Synthesis-3 / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Two level Boolean Logic Synthesis-3
Material type: Computer file Computer file; Format: electronic
Publication details: Guwahati Indian Insitiute of Technology
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656.
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Design Verification and Test of Digital VLSI Circuits: Heuristic Minimization of Two-Level Circuits / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Heuristic Minimization of Two-Level Circuits
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Publication details: Guwahati Indian Insitiute of Technology
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657.
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Design Verification and Test of Digital VLSI Circuits: Finite State Machine Synthesis / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Finite State Machine Synthesis
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Publication details: Guwahati Indian Insitiute of Technology
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658.
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Design Verification and Test of Digital VLSI Circuits: Multilevel Implementation / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Multilevel Implementation
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Publication details: Guwahati Indian Insitiute of Technology
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659.
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Design Verification and Test of Digital VLSI Circuits: Introduction to formal methods for design verification / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Introduction to formal methods for design verification
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Publication details: Guwahati Indian Insitiute of Technology
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660.
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Design Verification and Test of Digital VLSI Circuits: Temporal Logic: Introduction and Basic Operators / Jatindra Kumar Deka and Santosh Biswas by Series: NPTEL Lecture Series. Computer Science and Engineering Temporal Logic: Introduction and Basic Operators
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Publication details: Guwahati Indian Insitiute of Technology
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